Today’s quantum computers are held back by a tangle of bulky cables and electronics that cannot scale beyond about 50 qubits. This project aims to replace that clunky control hardware with compact, high-bandwidth components borrowed from modern telecommunications—optical fibres, wireless chips, and cryogenic CMOS electronics. Without such a redesign, quantum computers will never reach the hundreds of qubits needed to outperform classical machines on real problems. The problem is physical, not theoretical. Each qubit currently requires its own cable running into a cryogenic fridge, and that approach simply does not fit more than a few dozen qubits. By adapting existing ICT hardware, the researchers hope to shrink the control system, increase signal density, and make modular, scalable quantum processors possible. If successful, this work could unlock quantum computers with more than 100 qubits—enough to tackle problems in drug discovery, materials design, and cryptography that are intractable for classical computers. The project is not fundamental science; it is an engineering push to solve a specific bottleneck. It does not promise a new quantum algorithm or a discovery about quantum physics. Instead, it focuses on the unglamorous but essential task of building the wiring and control systems that make large-scale quantum computing physically possible.
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Quantum computers are superior to conventional computers for their high computing power, and this is true only if they have many qubits e.g., 100s or more. The current leading commercial players in the field have successfully demonstrated processors with more than 50 cryogenic qubits using the classical control interferences which suffer from bulky cables and electronics. Novel solutions are desperately and urgently required for qubit upscaling. Avenues for improvement include dramatically increasing the number, density and modularity of independent control channels, signal bandwidth, the time and amplitude resolution of generated waveforms, and the physical footprint of circuits and interconnects for noisy intermediate-scale quantum computing (NISQC), universal fault-tolerant quantum computing (UFTQC) and efficient multiplexing of single-photon detectors. This project will be a step towards improving the performance of and potentially revolutionising QC control hardware and future integration based on modern information and communication hardware. This will be achieved by synergising QC with ICT's state-of-the-art developments in optical, wireless and cyro-CMOS electronics. The researchers from both QC and ICT sectors will collaboratively identify, explore, develop, and benchmark the technologies at both device and system levels. Through nationwide networking chaired by NQCC with support from the University of Glasgow (UoG), National Quantum Computing Centre (NQCC), National Physical Laboratory (NPL), University College London (UCL), University of Strathclyde (UoS), and Science and Technology Facilities Council (STFC) and more than 20 industrial and academic partners, we will eventually deliver the ambitious objectives for the next generation of quantum computers with more than 100 qubits. The first 12 months of EPIQC will be dedicated to co-creation activities aimed at validating and further refining the focus of our work. The NQCC will devote a project manager to coordinate and support the co-creation activities, helping to reach the broader community and ensuring activities are delivered professionally. In the first instance, a series of one-to-one conversations will be held with end-users to validate needs and understand the market pull. This will inform further one-to-one discussions with key industry players and the identification of supply chains and pre-competitive areas of research. This groundwork will be essential to the successful set-up and definition of a series of focus groups on each of the pillars, exploring state-of-the-art, future trends and markets and defining top-level roadmaps for pre-competitive challenges. These challenges will be further explored through sandpits defining the details of research strands under each pillar. In years 2-4 EPIQC focusses on investigations of cross-disciplinary interfacing and integration of alternative control and readout architectures through three complementary pillars, and the verification of ICT-QC hardware for user needs.
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