Electronics already consume as much energy as the global aviation industry, and that share is climbing toward 10% of all CO₂ emissions by 2030. The core problem is the von Neumann bottleneck: shuttling data between separate logic and memory chips wastes power and slows processing. This project builds two-in-one devices—ferroelectric field-effect transistors (FeFETs) and tunnel electro-magneto-resistance (TEMR) devices—that perform both logic and memory functions on the same chip, cutting that energy waste. The team will use atomically thin semiconductors (transition metal dichalcogenide hetero-bilayers) and a recently developed wafer-scale dielectric (hexagonal boron nitride) to create ultra-clean interfaces, eliminating defects that cause instability. If successful, the work could produce transistors that switch with far less energy than today’s silicon counterparts and TEMR devices with magneto-resistance exceeding 1000%, tunable by the ferroelectric layer’s polarisation. The fabrication processes are designed to be compatible with existing CMOS manufacturing, so the technology could slot into industrial supply chains. For the UK, this directly supports the National Semiconductor Strategy’s goal of building a resilient local chip supply chain and contributes to net-zero emissions by 2050 through more efficient electronics.
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This proposal is underpinned by our recent discoveries: out of plane ferroelectricity in hetero-bilayers of atomically thin body (ATB) semiconductors (Science, 2022); and realisation of wafer scale growth of a universal dielectric in the form of hexagonal boron nitride (h-BN) (Nature, 2022). The ground-breaking nature of the proposed work is in realisation of ultra-low power devices - namely ferroelectric field effect transistors (FeFETs) and tunnel electro-magneto-resistance (TEMR) devices - using industrially relevant complementary metal oxide semiconductor (CMOS) compatible processes that can perform both logic and memory functions to increase the energy efficiency of electronics. The carbon footprint (3% of total CO2 emission) of modern electronics is comparable to that of aviation and is expected to rise to ~10% by 2030 because of the von Neumann bottleneck where information is shuttled between the logic and memory devices, which increases energy consumption and reduces the processing speed. One objective of the proposed work is to directly explore and therefore understand the key processes that underpin the stable operation of FeFETs based on ATB semiconductors to significantly accelerate their development. Second objective is to integrate ferroelectric hetero- bilayers as tunnel layers between two ferromagnetic contacts to realise TEMR devices with magneto-resistance of > 1000%. The advantage of TEMR devices is that the tunnelling probability can be tuned with polarisation of the ferroelectric tunnel layer so that very large MR is achievable. In applications that are of strategic importance for the UK, energy efficient electronics are fundamentally important for meeting the net zero by 2050 goal as well as developing resilient local supply chain for semiconductors. We propose to focus on hetero-bilayers of transition metal dichalcogenide (TMD) compounds as a novel class of ferroelectric semiconductors where probing and understanding of device operation can rapidly improve the quality and control of available devices beyond the state-of-the-art, and for which recent work has highlighted significant application potential for high performance electronics. The motivation for such new devices is to address today's most important scientific challenges, namely that of climate change through energy efficient high-performance electronics. The recently published Nation Semiconductor Strategy highlights the need to develop the UK market and local supply chains. Atomically thin semiconductors were pioneered in the UK and this proposal will leverage the local expertise to develop new technology. Specifically, we aim to: (i) Develop methodology for realising ultra-clean semiconductor/dielectric interface using our recent breakthrough in high quality wafer scale chemical vapor deposition (CVD) grown h-BN (Nature, 2022) to eliminate hysteresis due to interface defects. We will also integrate our ultra-clean van der Waals (vdW) contacts on ATBs [enabled via EPSRC funded research (EP/T026200/1) and reported in Nature 2019, 2022] to eliminate defects at metal/semiconductor junctions. (ii) Establish a fundamental understanding of ferro-magnetic (FM) vdW contacts for spin injection and tunnelling behaviour through ATB TMD ferroelectric hetero-bilayers. (iii) Develop an integrated and scalable CMOS compatible fabrication process for ultra-low energy FeFETs and TEMR devices based on wafer scale CVD grown ATB hetero-bilayers using h-BN dielectrics and vdW contacts. (iv) Explore transport properties of FeFETs and TEMR devices that are capable of functioning as both logic and memory devices to establish understanding of fundamental operating mechanisms and energy footprint. Establish new design concepts exploiting the logic and memory functions of FeFETs and TEMR devices for high performance, low power electronics.
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