Fault-tolerance in the near-term: advancing methods for practical quantum error correction

The first objective of the National Quantum Strategy (NQS) missions, published on 14th December 2023, is to enable the development of “UK-based quantum computers capable of running 1 trillion operations and supporting applications that provide benefits well in excess of classical supercomputers” [1]. At present, quantum computers are far from this objective: qubits are noisy, and approximately 1% of operations fail [2,3]. To fulfil the NQS missions, quantum computers need to be made fault-tolerant using quantum error correction (QEC). The essential principle underpinning QEC is that multiple noisy qubits can be combined to form so-called logical qubits. These logical qubits are robust against errors and will serve as the fundamental building block of arbitrarily scalable quantum computers. During this fellowship, my primary aim is to develop the tools and innovation required to integrate QEC into near-term quantum computing architectures. The National Quantum Computing Centre (NQCC) recently invested £30m in seven quantum computing testbed systems across a range of qubit technologies [4]. I will collaborate with the NQCC to design and deploy QEC protocols for each of the testbed devices. This will be the most extensive comparative assessment of fault tolerance in quantum computers to date. The experimental data gathered will be pivotal in guiding the NQCC in strategic decisions on which qubit technologies to support in the long term. Quantum computers must be built in tandem with classical co-processors to decode QEC measurement information before the qubits become irreversibly corrupted. For a full-scale quantum computer, QEC measurement information can be generated at rates of terabytes per second [5]. As such, access to high-performance decoders is critical. To alleviate the load on classical co-processors, I will develop low-power parallel decoding algorithms. Through a collaboration with the Edinburgh Parallel Computing Centre, I aim to implement these algorithms on specialised hardware such as GPUs, FPGAs, and RISC-V boards. To accelerate the transition to fault-tolerant quantum computing, it will be necessary to discover methods for reducing the overhead of QEC. I will conduct research into quantum low-density parity check (QLDPC) codes as a resource-efficient alternative to surface code QEC. To this end, I will leverage existing expertise from classical communications technology to design QLDPC protocols for near-term quantum hardware. Further to this, I will develop improved methods for performing QLDPC encoded computation and conduct resource estimations for practical quantum algorithms. These new QEC protocols, as well as their benchmarks, will be made publicly available through an online database. Given the steep learning curve for newcomers to QEC, there is a pressing need for intuitive software that simplifies the exploration and evaluation of fault-tolerant protocols. To address this, I will develop user-friendly design automation tools to streamline the incorporation of QEC into the quantum computing stack. In the first instance, I will develop an end-to-end QEC compiler that automatically translates a high-level description of a quantum algorithm to a fault-tolerant circuit. This will simplify the process of fault-tolerant design and accelerate the rate at which new QEC protocols are deployed in hardware.