Quantum computers today can barely perform a few dozen error-free operations before mistakes creep in, but the UK government wants one million by 2028 and a trillion by 2035. OQC-Riverlane is building a quantum processor that catches and corrects its own errors—specifically a type called leakage errors—while running inside a commercial data centre alongside classical supercomputers. The core problem is that quantum operations are fragile. Even tiny disturbances cause errors that multiply, making calculations useless. Current error correction methods require enormous numbers of extra qubits, which is impractical. This project tackles the leading cause of errors directly at the hardware level, then tests the corrections on real machines rather than just in simulations. If successful, the project will produce the first quantum error correction testbed integrated with high-performance computing in a secure data centre. That would be a practical step toward fault-tolerant quantum computers—machines that could eventually crack encryption, simulate new materials, or optimise supply chains. For now, the immediate impact is a working demonstrator by March 2026 that shows whether hardware-efficient error correction can actually function outside a laboratory.
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The UK Government has set its ambitious target to national industry and academia of achieving 1 million quantum operations (the MegaQuop) by 2028 and 1 trillion quantum operations (TeraQuop) by 2035 through its Quantum Mission. The key challenge today to reach this computational advantage is how we build Quantum Computers (QCs) capable of large numbers of error free quantum operations, or quops. OQC-Riverlane proposes to conduct a major programme of work building on existing efforts around novel qubit design, error correction, and datacentre integration. Brought together, we aim to demonstrate hardware-efficient quantum error correction (QEC) techniques in a commercial datacentre environment; serving as a testbed for further QEC development that takes advantage of QEC-optimisation across the computing stack. QEC capabilities tested on real hardware in a real commercial environment is key towards achieving the UK's Quantum Mission 1 goal. Our core work packages centre around three core objectives: * The demonstration of a QEC-optimised quantum processor. The first of its kind Quantum Processing Unit (QPU) which incorporates leakage error detection for improved performance with increased hardware-efficiency. * The operationalisation of the first QEC testbed, integrated with High Performance Compute (HPC), within a secure datacentre environment. This first of its kind integration would not only represent a great technical development towards the quantum missions, but also a key step in the commercialisation of quantum computing hardware. * To facilitate the above, the development of fault-tolerant QEC decoding and resource estimations incorporating real-world noise models of QEC-optimised quantum processors. Using co-located classical compute, the project will also develop a digital twin that lives next to the real hardware to enable QEC testing across the quantum computer stack to identify bottlenecks and implement optimisations. Together, these work packages target fault tolerant quantum error correction by isolating the leading cause of errors and incorporating hardware-efficient error correcting protocols. These will be incorporated into an operational demonstrator within a datacentre environment by the end of March 2026\.
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