Completed Physics & Astronomy Computing & AI

HERMES - Highly Enhanced Real-time Metrics for Error-corrected Superconducting quantum computers

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A UK-based team is upgrading a superconducting quantum computer to run error correction in real time, not just after the fact. Today’s quantum computers are too error-prone to solve useful problems. The core fix—quantum error correction (QEC)—requires a classical control system to detect and fix errors faster than new ones appear. Current systems are too slow and inaccurate to keep up. This project tackles that bottleneck by upgrading Rigetti’s quantum processor at the UK National Quantum Computing Centre, integrating Riverlane’s error-correction stack, and testing whether the combined system can meet the speed, latency, and accuracy demands of real-time QEC. If successful, the work will demonstrate a mandatory capability for fault-tolerant quantum computing—the ability to run many operations without accumulating errors. That would move quantum machines from laboratory curiosities toward practical tools for drug discovery, materials design, and logistics optimisation. The project also feeds directly into the UK’s goal of running a large number of quantum operations on a domestic machine, advancing both hardware and skills in the UK. A US-based Rigetti system will be used in parallel to avoid downtime during the UK upgrade.

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Fault-tolerant quantum computing promises to usher in a new era of high-performance computing, offering unprecedented power to solve several significant real-world problems. However, to effectively integrate quantum error orrection (QEC)---the cornerstone of fault tolerance---critical challenges must be addressed. These include processing bottlenecks in classical control systems and their integration with quantum error decoding technology, as well as the high error rates of current quantum computers. In this project, we aim to make measurable advancements towards overcoming these challenges, contributing to the UK Quantum Mission 1 by developing key capabilities required for executing a large number of quantum operations on a UK-based quantum computer. This project, a collaborative effort involving Rigetti, Riverlane, and the NQCC Superconducting Circuits Team, will focus on benchmarking and enhancing the QEC capabilities of superconducting quantum computers, leveraging Rigetti's superconducting quantum computing testbed hosted at the UK National Quantum Computing Centre (NQCC). Rigetti will upgrade the testbed by deploying a larger and higher-performing Quantum Processing Unit (QPU) and enhancing the control systems, which will be integrated with Riverlane's QEC stack. Riverlane will lead the QEC experiments, identifying key improvements to enhance system performance and meet crucial QEC metrics. The NQCC Superconducting Circuits Team will support system upgrades and ensure quality assurance for QEC experiments. Additionally, one of Rigetti's systems hosted in the US---remotely accessible by Rigetti UK, Riverlane, and the NQCC Superconducting Circuits Team---will be available throughout the project to accelerate progress, mitigating downtime during the UK system upgrade and enabling parallel execution of technical activities in the project's second phase. Findings from the joint research are also expected to inform the design and fabrication of enhanced QPUs, particularly to improve mid-circuit measurement and driven passive reset capabilities. The impacts on QEC performance of newly fabricated QPUs, following the enhancements, will also be evaluated as part of the project. The project aims to conduct ambitious QEC tests that advance state-of-the-art metrics, including throughput, latency, and decoding accuracy. Critically, it seeks to demonstrate real-time QEC capabilities---a mandatory requirement for universal, fault-tolerant quantum computation. The NQCC Superconducting Circuits Team's direct involvement and the use of Rigetti's testbed at the NQCC will further advance quantum skills and hardware development in the UK.

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Related Research

Grants with similar aims, by meaning.

Fault-tolerance in the near-term: advancing methods for practical quantum error correction
DECIDE: Dimon Error Correction Integrated into a Data-centre Environment.
QEC Readout Testbed – SEEQC’s scalable digital QEC ready qubit readout chip integrated with Rigetti’s Novera QPU
SiQEC - Silicon Quantum Error Correction
Empowering Practical Interfacing of Quantum Computing (EPIQC)

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Collaborative R&D

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