A silicon chip will run repeated rounds of quantum error correction for the first time, using spin qubits fabricated on standard 300mm semiconductor production lines. Quantum computers are notoriously fragile. The quantum bits, or qubits, that store and process information are easily disturbed by environmental noise, which introduces errors. Without a way to detect and fix these errors, any calculation longer than a few operations will fail. Error correction is the only known route to a reliable, large-scale quantum computer, but it has never been demonstrated in silicon spin qubits. If SiQEC succeeds, it will show that silicon—the same material used in every smartphone and laptop—can host a fault-tolerant quantum processor. The project targets two breakthroughs: repeated error-correction cycles on a two-dimensional qubit array, and high-fidelity shuttling of individual spins between cells. Together, these capabilities would unlock a path to systems with millions of qubits. The UK’s National Quantum Strategy aims for 1 trillion error-corrected quantum operations by 2035; this project directly supports that goal. Practical applications—such as simulating new materials, optimising energy grids, or designing more efficient supply chains—would become feasible only after such error-corrected systems exist.
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The SiQEC (Silicon Quantum Error Correction) project aims to deliver the first demonstration of a spin-based quantum computing system capable of implementing repeated rounds of quantum error correction (QEC) - a critical milestone toward fault-tolerant quantum computing. This collaboration between Quantum Motion and University College London will introduce key technological innovations including two-dimensional qubit connectivity, fast quantum non-demolition parity measurements, and high-fidelity spin qubit shuttling. Our approach leverages silicon spin qubits created using standard 300mm semiconductor manufacturing processes, offering an inherently scalable path to large quantum systems. The quantum processing unit (QPU) will be based on a unit cell containing a 2×3 quantum dot arrangement with nearest-neighbor interactions, comprising two data qubits, a measure qubit, and an ancilla qubit for readout. This architecture enables non-demolition parity measurements to detect either bit-flip or phase-flip errors while preserving quantum states. The project builds on our demonstrated capabilities in silicon spin control, including high-fidelity single qubit gates (\>99%), two-qubit gates (98%, a world-leading demonstration of the first exchange control in qubits fabricated in natural silicon on a 300mm wafer scale), and compact readout (\>99.9%). We will progress through systematic development phases: first implementing QEC cycles on our existing linear qubit arrays, then advancing to an improved system with two-dimensional connectivity. In parallel, we will develop and demonstrate spin qubit shuttling, a key capability for connecting QEC unit cells, which will be a world first in silicon metal-oxide-semiconductor (MOS) devices. What sets this project apart is its combination of two revolutionary advances: 1) First demonstration of repeated QEC cycles in silicon spin qubits building on novel two-dimensional qubit topology, and 2) First demonstration of high-fidelity spin shuttling in silicon for inter-cell connectivity. These capabilities are essential for realizing proposed fault-tolerant architectures that could scale to the millions of qubits needed for quantum advantage. The project directly supports the UK's National Quantum Strategy goal of enabling 1 trillion quantum operations in error-corrected systems by 2035\. By demonstrating fundamental error correction in a scalable semiconductor platform, SiQEC will accelerate progress toward fault-tolerant quantum computers capable of solving practical problems beyond classical computational capabilities. This work leverages the UK's leadership in silicon quantum computing while strengthening its position in the global race to achieve quantum advantage.
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