Completed Materials & Manufacturing Cells, Biochemistry & Physiology

Design for Manufacturability of High Voltage Ics on SOI for automotive applications

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Cars are getting smarter, but their electronics need to handle higher voltages without overheating or shorting out—and this project found a way to build those chips more reliably. The HIVICS project tackled a fundamental manufacturing problem: how to pack high-voltage transistors and control circuits onto a single silicon chip without them interfering with each other. Standard silicon chips struggle with heat buildup and electrical leakage when voltages climb. The team used Silicon on Insulator (SOI) substrates—a layered wafer design that insulates components—and optimised them through computer simulations. They developed novel Compound Buried Layers that improve heat flow and reduce unwanted capacitance, and created patterned Tungsten Silicide layers for even better performance. They also built accurate 3D thermal models to predict how neighbouring transistors heat each other, and a stress model to prevent cracking during oxidation. If this research succeeds, it could make power electronics in electric vehicles, hybrid cars, and communications infrastructure more efficient and durable. The chips would run cooler, waste less energy, and last longer—improving systems most drivers never think about, but that quietly keep modern vehicles safe and responsive.

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The HIVICS project has demonstrated high voltage complementary Bipolar and MOS IC technologies integrated on Silicon on Insulator (SOI) substrates to achieve high performance and high area efficiency power devices for automotive and communication market applications. To address the conflicting demands of electrical isolation, thermal management, stress, high-packing density and low on-resistance, advanced device architectures and novel SOI substrates were optimised for performance and manufacturability using advanced Technology Computer Aided Design (TCAD) simulations. Novel Compound Buried Layers SOI substrates have demonstrated improved thermal conductivities and capacitances. Patterned buried Tungsten Silicide layers in SOI substrates have been developed for further performance improvements. Accurate 3D modelling of thermal resistance of Bipolar devices on SOI was developed to create a circuit model that describes the thermal interaction between neighbouring cells. A stress mediated oxidation model was developed and implemented into a 3D TCAD stress simulation tool and this was calibrated with measurements of Local Oxidation of Silicon (LOCOS) and Deep Trench Isolation structures.

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Collaborative R&D

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