Today’s quantum computers slow down and make more errors as they grow larger, because they struggle to shuttle information around the chip. The Q-TATA project tackles this qubit routing bottleneck by moving trapped-ion processors from a 1D chip layout to a 2D one. In a 10,000-qubit system, that shift could cut runtime by a factor of a million. The consortium—Oxford Ionics, Bay Photonics, and Riverlane—brings together world-record gate fidelities, advanced chip packaging, and quantum error correction tools to make the 2D design commercially viable. If successful, the work directly supports the UK’s 2035 Quantum Mission: building a quantum computer capable of one trillion operations, outperforming classical supercomputers in sectors such as drug discovery, materials design, and logistics optimisation. For now, the research is squarely applied—it targets a specific engineering barrier to scaling quantum hardware, not fundamental science. The payoff is a faster, more reliable quantum processor that can run useful algorithms, rather than remaining a lab curiosity.
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**"Quantum Testbed Advancements through 2D Trapping Architectures" (Q-TATA)** solves a barrier to scaling quantum computers: the qubit routing challenge. Existing Quantum Computers (QCs) become slower and more prone to errors as they scale due to limited ability to efficiently move information around the processors. Solving this challenge is a key enabler for the UK's 2035 Quantum Mission, which aims to develop accessible quantum computers capable of executing 1 trillion operations---outperforming classical supercomputers in key economic sectors. To unlock the commercial impact of quantum computing, today's small-scale devices must be scaled into powerful quantum supercomputers capable of running algorithms efficiently. Achieving this with the speed and performance required for commercial applications will require significant improvements in the ability of existing processors to move information around the chip, a process known as qubit routing. Qubit routing is thus a key bottleneck in scaling QCs. **Q-TATA addresses this challenge** by enabling highly efficient routing in ion-trap systems with proven world-record gate fidelity. Trapped ions are the most powerful QCs, measured by Quantum Volume. However, all existing trapped-ion QCs utilise 1D chip designs with limited ability to route qubits around the chip, with runtimes and errors increasing quadratically with the qubit count. Extending this layout to 2D significantly reduces runtime by up to 6 orders of magnitude in 10,000-qubit systems. Proof-of-concept work by Oxford Ionics has validated this approach, but scalable commercial deployment demands innovation in trap design and packaging, followed by innovation in Quantum Error Correction (QEC) to utilise the 2D designs. **To realise this ambitious project**, we bring together a unique consortium capable of advanced chip designs, the fabrication and packaging techniques for manufacturing them, and QEC. * OI has world-leading in-house expertise in ion trap design, routing, and high-fidelity gates (demonstrated single-qubit 99.99916% and two-qubit 99.97%) * Bay Photonics pioneers advanced packaging solutions for quantum technologies, providing existing and novel techniques required to realise the electrical, photonic and electrostatically shielded packaging of high-density quantum devices. * Riverlane develops cutting-edge tools for QEC that support hardware companies in architectural design choices for efficient QEC. The technology will be optimised for fault-tolerant operation required to achieve the Quantum Missions goal.
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