QEC Readout Testbed – SEEQC’s scalable digital QEC ready qubit readout chip integrated with Rigetti’s Novera QPU

Quantum computers need to detect and fix their own errors faster than those errors can multiply, or the machines will never be powerful enough to be useful. Current quantum computers are too error-prone to run the complex calculations that would justify their existence. The fundamental problem is that quantum information is fragile and degrades in microseconds. To correct errors, a quantum computer must read the state of special "syndrome" qubits, process that information, and apply corrections—all before errors cascade. This readout step is the critical bottleneck preventing scale-up. This project integrates SEEQC’s digital readout chip with Rigetti’s existing quantum processor to create a complete testbed system. The aim is to demonstrate a readout pathway fast and accurate enough to support one million quantum operations—the UK government’s 2028 target—and eventually a trillion operations by 2035. If successful, the work removes a key engineering barrier to practical quantum computing. That would matter for any field that depends on simulating complex systems: drug discovery, materials design, cryptography, and optimisation of energy grids or supply chains. For now, the research is squarely about solving a hardware bottleneck, not about a specific application.